? 2000 fairchild semiconductor corporation ds006611 www.fairchildsemi.com august 1986 revised february 2000 dm9602 dual retriggerable, resettable one shots dm9602 dual retriggerable, resettable one shots general description these dual resettable, retriggerable one shots have two inputs per function; one which is active high, and one which is active low. this allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. when input condi- tions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. the retriggerable feature permits output pulse widths to be extended. in fact a continuous true out- put can be maintained by having an input cycle time which is shorter than the output cycle time. the output pulse may then be terminated at any time by applying a low logic level to the reset pin. retriggering may be inhibited by either connecting the q output to an active high input, or the q output to an active low input. features n 70 ns to output width range n resettable and retriggerable0% to 100% duty cycle n ttl input gatingleading or trailing edge triggering n complementary ttl outputs n optional retrigger lock-out capability n pulse width compensated for v cc and temperature vari- ations ordering code: connection diagram function table h = high voltage level l = low voltage level x = don't care logic diagrams order number package number package description dm9602n n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide pin numbers operation abclr h ? l l h trigger hl ? h h trigger xxl reset
www.fairchildsemi.com 2 dm9602 operating rules 1. an external resistor (r x ) and external capacitor (c x ) are required as shown in the logic diagram. 2. the value of c x may vary from 0 to any necessary value available. if, however, the capacitor has leakages approaching 3.0 m a or if stray capacitance from either terminal to ground is more than 50 pf, the timing equa- tions may not represent the pulse width obtained. 3. the output pulse with (t) is defined as follows: where: r x is in k w , c x is in pf t is in ns for c x < 10 3 pf, see figure 1. for k vs. c x see figure 6. 4. if electrolytic type capacitors are to be used, the follow- ing three configurations are recommended: 1. use with low leakage capacitors: the normal rc configuration can be used predict- ably only if the forward capacitor leakage at 5.0v is less than 3 m a, and the inverse capacitor leakage at 1.0v is less than 5 m a over the operational tem- perature range. r < 0.6 r x (max) 2. use with high inverse leakage current electrolytic capacitors: the diode in this configuration prevents high inverse leakage currents through the capacitor by preventing an inverse voltage across the capacitor. the use of this configuration is not recommended with retriggerable operation. t ? 0.3 rc x 3. use to obtain extended pulse widths: this configuration can be used to obtain extended pulse widths, because of the larger timing resistor allowed by beta multiplication. electrolytics with high inverse leakage currents can be used. r < r x (0.7) (h fe q1) or < 2.5 m w , whichever is the lesser r x (min) < r y < r x (max) (5 k w r y 10 k w is recommended) q1: npn silicon transistor with h fe requirements of above equations, such as 2n5961 or 2n5962. t ? 0.3 rc x this configuration is not recommended with retriggerable opera- tion. 5. to obtain variable pulse width by remote trimming, the following circuit is recommended: 6. under any operating condition, c x and r x (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. 7. input trigger pulse rules (see triggering truth table) input to pin 5(11), (pin 3(13) = high) pin 4(12) = low t 1 , t 3 = min. positive input pulse width > 40 ns t 2 , t 4 = min. negative input pulse width > 40 ns input to pin 4(12) (pin 3(13) = high) pin 5(11) = high 8. the retriggerable pulse width is calculated as shown below: the retrigger pulse width is equal to the pulse width (t) plus a delay time. for pulse widths greater than 500 ns, t w can be approximated as t. retriggering will not occur if the retrigger pulse comes within ? 0.3 c x (ns) after the initial trigger pulse (i.e., during the discharge cycle). 9. reset operationan overriding clear (active low level) is provided on each one shot. by applying a low to the reset, any timing cycle can be terminated or any new cycle inhibited until the low reset input is removed. trigger inputs will not produce spikes in the output when the reset is held low. 10. v cc and ground wiring should conform to good high frequency standards so that switching transients on v cc and ground leads do not cause interaction between one shots. use of a 0.01 to 0.1 m f bypass capacitor between v cc and ground located near the dm9602 is recommended. note 1: for further detailed device characteristics and output performance, please refer to the nsc one-shot application note, an-366.
3 www.fairchildsemi.com dm9602 typical performance characteristics figure 1. output pulse width vs. timing resistance and capacitance for c x < 10 3 pf figure 2. normalized output pulse width vs. ambient temperature figure 3. pulse width vs. timing resistor figure 4. normalized output pulse width vs. supply voltage figure 5. minimum output pulse width vs. ambient temperature figure 6. typical k coefficient variation vs. timing capacitance
www.fairchildsemi.com 4 dm9602 absolute maximum ratings (note 2) note 2: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will define the conditions for actual device operation. recommended operating conditions electrical characteristics over recommended operating free air temperature range (unless otherwise noted) note 3: unless otherwise noted, r x = 10k for all tests. note 4: all typicals are at v cc = 5v, t a = 25 c. note 5: ground pin 1(15) for v ol on pin 7(9) or v oh and i os on pin 6(10) and apply momentary ground to pin 4(12). open pin 1(15) for v ol on pin 6(10) or v oh and i os on pin 7(9). note 6: not more than one output should be shorted at a time. supply voltage 7v input voltage 5.5v operating free air temperature range 0 c to + 70 c storage temperature range - 65 c to + 150 c symbol parameter min nom max units v cc supply voltage 4.75 5 5.25 v v ih high level t a = - 55 c input voltage t a = 0 c1.9 t a = 25 c1.8 v t a = 75 c1.65 t a = 125 c v il low level t a = - 55 c input voltage t a = 0 c0.85 t a = 25 c0.85v t a = 75 c0.85 t a = 125 c i oh high level output current - 0.8 ma i ol low level output current 16 ma t a free air operating temperature 0 75 c symbol parameter conditions (note 3) min typ max units (note 4) v i input clamp voltage v cc = min, i i = - 12 ma - 1.5 v v oh high level v cc = min, i oh = max 2.4 v output voltage v il = max, v ih = min (note 5) v ol low level v cc = min, i ol = max 0.45 v output voltage v il = max, v ih = min (note 5) i ih high level input current v cc = max, v i = 4.5v 60 m a i il low level v cc = max v i = 0.45v - 1.6 ma input current v cc = min v i = 0.45v - 1.41 i os short circuit output current v cc = max, v out = 1v (note 5)(note 6) - 35 ma i cc supply current v cc = max 39 50 ma
5 www.fairchildsemi.com dm9602 switching characteristics v cc = 5v, t a = 25 c symbol parameter conditions min max units t plh propagation delay time, negative trigger input c l = 15 pf 40 ns low-to-high level output to true output c x = 0 t phl propagation delay time, negative trigger input r x = 5 k w 48 ns high-to-low level output to complement output t pw (min) minimum true output 100 pulse width ns minimum complement 110 pulse width t pw pulse width r x = 10 k w 3.08 3.76 m s c x = 1000 pf c stray maximum allowable wiring pins 2, 14 to gnd 50 pf capacitance r x external timing resistor 550k w
www.fairchildsemi.com 6 dm9602 dual retriggerable, resettable one shots physical dimensions inches (millimeters) unless otherwise noted 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide package number n16e fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
home >>> products >>>dm9602 [information as of 1-aug-2000] dm9602 dual retriggerable resettable one shots generic p/n 9602 contents general description features datasheet availability, models, samples & pricing application notes general description these dual resettable, retriggerable one shots have two inputs per function; one which is active high, and one which is active low. this allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. when input conditions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. the retriggerable feature permits output pulse widths to be extended. in fact a continuous true output can be maintained by having an input cycle time which is shorter than the output cycle time. the output pulse may then be terminated at any time by applying a low logic level to the reset pin. retriggering may be inhibited by either connecting the q output to an active high input, or the q# output to an active low input. features 70 ns to ? output width range resettable and retriggerable-0% to 100% duty cycle ttl input gating-leading or trailing edge triggering complementary ttl outputs optional retrigger lock-out capability pulse width compensated for v cc and temperature variations pdf contact fairchild search tools products what's new company product folder fairchild logo 1 of 2 8/4/00 2:56 pm fairchild p/n dm9602 - dual retriggerable resettable one shots file:////roarer/root/data13/imaging/bit...0804/08032000/fair/08022000/dm9602.html
datasheet receive datasheet via e-mail or download now ; use adobe acrobat to view... dm9602 dual retriggerable resettable one shots (84 kbytes; 29-jul-00) availability, models, samples & pricing part number grade package status models budgetary pricing std pack size package marking type # pins spice ibis quantity $us ea dm9602n comm mdip 16 full production n/a n/a 1-24 25-99 100-1000 $2.67 $2 $1.60 n/a $y&z&4&t&p dm9602n DM9602CW comm wafer preliminary n/a n/a n/a n/a application notes receive document via e-mail or download now ;use adobe acrobat to view... an-372: designer's encyclopedia of bipolar one-shots (447 kbytes; 29-jul-00) quick search company what's new products search tools contact fairchild home copyright 2 of 2 8/4/00 2:56 pm fairchild p/n dm9602 - dual retriggerable resettable one shots file:////roarer/root/data13/imaging/bit...0804/08032000/fair/08022000/dm9602.html
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